US Patent 7453117 Non-volatile semiconductor memory device

To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.