Patent attributes
The present application describes techniques for determining maximum acceptable modeled load latency (e.g., a model number of clock cycles required between the time a load issues and the time its use can issue) for instruction scheduling which uses less compile time, on the order of log2 (Maximum load latency—Minimum load latency). Typically, during instruction scheduling, register pressure is monotonically non-decreasing with respect to the scheduled load latency. Therefore, in some embodiments, a hierarchical search method is used to determine the acceptable schedule with the largest modeled load latency. According to an embodiment, a binary search is employed which reduces the compile time required to determine maximum load latency for which registers can be assigned.
