Patent attributes
A display control apparatus has a synchronizing signal generating section which generates a display synchronizing signal, a bus access control section which reads out video data for a plurality of system, one system at a time, from a local memory, a screen combining section which processes to combine video data which was readout, and video data for use in combining, sequentially, a buffer section which stores video data which was processed to be combined, and the video data for use in combining, a buffer control section which controls an access to the buffer section, a display IF section which reads out video data that the buffer section stores, and outputs the video data to each of display monitors in accordance with a display synchronizing signal, and display output selecting means which selects an output destination of video data for plural systems, which the display IF section outputs.
