US Patent 7457142 Semiconductor memory device

A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. Agate of the first selecting transistor is connected to the 2·N−1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.