US Patent 7457164 Semiconductor memory device and electronic apparatus

In the semiconductor storage device, in a read operation, a bit line charging/discharging section 101 performs discharge of bit lines of a memory cell array 100, and a counter counts discharge periods over which the potentials of bit lines come to a specified potential, based on a comparison result of a comparator comparing a potential of a bit line with a reference potential. Based on the comparison result, a reference value generation section 104 generates a reference value (RCi) for determining information stored in each of the memory cells. The above count value (CBUSi) and the above reference value (RCi) are compared with each other by a data decision circuit 108. Based on the comparison result, an output data control circuit 109 outputs information stored in each of the memory cells. This semiconductor storage device suppresses increases in chip area and power consumption and outputs memory cell information accurately.