US Patent 7457190 Data latch controller of synchronous memory device
All edits
Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the control signals being synchronized with rising and falling edges of the divided signal; and a latch unit for latching data corresponding to the bits by means of the control signals, and outputting the data for the detection and amplification of the data. The data input circuit may include a first delay unit for delaying the data in order to match setup-hold time, a second delay unit for performing delay for adjusting the data outputted from the latch unit, and a third delay unit for performing delay for adjusting the write strobe signal outputted from the latch unit.
US Patent 07457190 Data latch controller of synchronous memory device US Patent 7457190 Data latch controller of synchronous memory device
US Patent 07457190 Data latch controller of synchronous memory device
Find more entities like US Patent 7457190 Data latch controller of synchronous memory device
