Patent attributes
An interference detecting circuit for use in an ATSC system and for detecting interference of an ATSC signal includes: a buffering module for delaying to output a first PN63 synchronization format data when receiving the first PN63 synchronization format data; a correlation arithmetic circuit coupled to the buffering module for receiving the ATSC signal and performing a correlation operation on a second PN63 synchronization format data and the delayed first PN63 synchronization format data to output a detection signal when receiving the second PN63 synchronization format data; and a determining circuit for determining whether performing interference rejection on the ATSC signal or not according to the result of the above-mentioned correlation operation.