US Patent 7460405 Method for controlling nonvolatile memory device

Data is written to a nonvolatile memory device having a memory region of four bits or larger in one memory cell sandwiched by a source and a drain with an improved accuracy. The nonvolatile memory device 100 includes four control gates 114 to 117 provided between a first and a second impurity-diffused regions 106a and 160b that are provided separately from the semiconductor substrate, and a memory cell including memory regions 106a to 106d that are counterpart of the control gates. A method for controlling the nonvolatile memory device 100 includes classifying the four control gates 114 to 100 into two groups of right and left sides, and then, applying a lower voltage to an impurity-diffused region that is further from a target memory region for injecting an electron and applying a higher voltage to an impurity-diffused region that is closer the target memory region, and moreover applying a higher voltage, the higher voltage being higher than voltages applied to other control gates.