US Patent 7461212 Non-inclusive cache system with simple control operation

A cache system includes a processing device operative to access a main memory device, a primary cache coupled to the processing device and accessible from the processing device at faster speed than the main memory device, and a secondary cache coupled to the processing device via the primary cache and accessible from the processing device at faster speed than the main memory device, wherein the primary and secondary caches are configured such that first data is stored as a data entry in each of the primary and secondary caches when the first data is read from the main memory device in response to access from the processing device, and such that second data in the secondary cache is invalidated without invalidating the second data in the primary cache when a need arises to invalidate the second data in the secondary cache in response to access from the processing device.