Patent attributes
First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to form a first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.