US Patent 7464307 High performance serial bus testing methodology

Patent 7464307 was granted and assigned to Intel on December, 2008 by the United States Patent and Trademark Office.

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Patent Inventor Names

Andrew W. Martwick0

David G. Ellis0

Jay J. Nejedlo0

Mike Wiznerowicz0

Richard J. Glass0

Theodore Z. Schoenborn0

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Patent abstract

According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

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Patent Citations Received

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US Patent 11662381 Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers

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