US Patent 7466619 Semiconductor memory device

A semiconductor memory device includes a plurality of banks #0 to #3, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.