US Patent 7467337 Semiconductor memory device

Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.