US Patent 7470605 Method for fabrication of a MOS transistor

Disclosed is a method for fabricating a MOS transistor. The present method includes the steps of: (a) forming a gate electrode including a gate insulating layer and a polysilicon gate conductive layer on an active region in a semiconductor substrate; (b) forming a metal layer over the substrate including the gate electrode; (c) heat-treating the substrate to form a polycide layer on a top surface and sidewalls of the gate electrode; (d) removing an unreacted portion of the metal layer; (e) removing the polycide layer from the top surface and sidewalls of the gate electrode, thus reducing a width of the gate electrode; and (f) forming source and drain regions in the active region adjacent to the gate electrode.