A device comprising an integrated circuit including at least one circuit block having an operating mode controlled in response to an enable signal or a clock signal. The circuit block receives a load current to power the circuit block, an amplitude of the load current being a function of the operating mode of the circuit block. The integrated circuit includes a weighting circuit to generate a weighting signal to indicate an expected amplitude of the load current of the integrated circuit. The weighting circuit monitors at least one of the enable signal and the clock signal and determines the expected amplitude of the load current as a function of the at least one of the enable signal and the clock signal.