Patent attributes
A logic circuit described in the netlist style HDL and a lower-level logic circuit (lower-level module) of a library which corresponds to an instance in the logic circuit and is described in the RTL style are read to a logic circuit storage unit by a logic circuit reading unit. A library hierarchical expansion unit performs a process of expanding a hierarchy of the library with respect to the instance in the logic circuit and converts it to the RTL style. An assignment statement eliminating unit replaces and eliminates an assignment statement in the logic circuit, which is converted to the RTL style. A logic circuit output unit outputs the logic circuit, which has undergone the conversion, in the RTL style. If the logic circuit of the library is described in the netlist style HDL, it is converted to an RTL style HDL as well as the case of the logic circuit.
