Patent attributes
First to fourth gate driver ICs G1 to G4 to be connected to a gate line 18 of a drive element 21 are arranged along a side of a liquid crystal display 2. Along a side of the first to four gate driver ICs G1 to G4, a FPC 5 for receiving signals is arranged. A first bus line 15 that branches between the first and second gate driver ICs G1 and G2 connects gate-low terminals 11b and 11a of the first and second gate driver ICs G1 and G2, respectively, to the FPC 5. A second bus line 16 that branches between the third and fourth gate driver ICs G3 and G4 connects gate-low terminals 11b and 11a of the third and fourth gate driver ICs G3 and G4, respectively, to the FPC 5. Gate-high terminals 10b and 10a, logic terminals 12b and 12a, and signal terminals 13 of the second and third gate driver ICs G2 and G3 are connected to the FPC 5. Gate-high terminals 10a and 10b, logic terminals 12a and 12b, and signal terminals 13 of the first and fourth gate driver ICs G1 and G4 are connected to corresponding terminals of the second and third gate driver ICs G2 and G3.
