Patent attributes
A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy cell group including first dummy cells, a dummy word line which selects the first dummy cell group, a dummy bit line to which data of the first dummy cell group is transferred, a generation circuit which generates an activation signal to activate the sense amplifier circuit based on a variation in a potential level of the dummy bit line, and a potential generating circuit which generates a first source potential applied to the first dummy cell group. The first source potential is different from a power supply potential.
