US Patent 7478358 Semiconductor integrated circuit device

LSI device 100 is provided with standard cell regions 10, a plurality of standard cells 20, memory blocks 11 and a plurality of memory cells 21. Standard cells 20 are equal in height “Hs” and disposed in standard cell regions 10 in a vertical direction. Memory blocks 11 are provided in contact with standard cell region 10 in a horizontal direction and memory cells 21 are disposed in memory blocks 11 in the vertical direction. Height “Hm” of memory cells 21 is equal to the height “Hs” or the height of the standard cell divided by an integer. Boundary positions of standard cells 20 neighboring each other are consistent with those of memory cells 21 neighboring each other.