US Patent 7479437 Method to reduce contact resistance on thin silicon-on-insulator device

A method of reducing contact resistance on a silicon-on-insulator includes exposing sidewalls and a portion of a top surface of a source/drain region of the device, forming a porous silicon layer within a surface of the source/drain region, implanting dopants in the source/drain region, and forming a silicide layer over the source/drain region. The porous silicon layer is formed by forming a layer of p+ doping on the exposed sidewalls and portion of the top surface of the source/drain region, forming a nitride liner over the device, including the source/drain region and the layer of p+ doping, forming a planarized resist over the nitride liner, recessing the planarized resist and etching the nitride liner to expose portions of the source/drain region, and forming the porous silicon layer on the exposed portions of the source drain region.