Patent attributes
A data transfer controller for transferring display data to N individual (where N is an integer, N≧2) display devices is disclosed. The data transfer controller includes a clock signal generating means, and a timing control means. The clock signal generating means generates clock signals. The timing control means adjusts the timing of the vertical synchronization signals included in the display data based on the clock signal for N individual display devices. The timing control means adjusts the timing of the vertical synchronization signals such that no vertical blanking period overlaps any other vertical blanking period, or adjusts the timing of the vertical synchronization signals such that no vertical display period overlaps a vertical display period of another display device among the display data transferred to each display device.
