US Patent 7483107 Array substrate and display panel having the same

An array substrate includes storage lines, a first pixel portion, a second pixel portion, a third pixel portion and a fourth pixel portion. The storage lines divide a region into a first pixel area, a second pixel area, a third pixel area and a fourth pixel area. Two gate lines and two data lines define the region. The two gate lines are adjacent and substantially parallel to each other. The two data lines are adjacent and substantially parallel to each other. The first, second, third and fourth pixel portions are formed in the first, second, third and fourth pixel areas, respectively.