Patent attributes
Disclosed is a memory device which can minimize a reduction in area efficiency even when the memory device has a small storage capacity and which can hide the access time to a row line. The memory device comprises: a matrix of a plurality of memory cells, each of which is connected to an intersection of each bit line of a plurality of pairs of bit lines and each word line of a plurality of word lines which intersect the bit lines; a plurality of sense amplifiers capable of read and write operations independently of one another, which are disconnectedly connected in parallel with the plurality of memory cells connected to the pairs of bit lines, through the pairs of bit lines; and a read gate and a write gate which are connected to each of the plurality of sense amplifiers connected in parallel with the pairs of bit lines, wherein the memory device is controlled so that read data is read out successively, when a word line to be activated, of the plurality of word lines is switched to another word line to be activated.
