Patent attributes
A stacked dual MOSFET package is disclosed. The package includes a first conductive tab; a high side MOSFET die coupled to the first conductive tab such that a drain of the high side MOSFET die is electrically coupled to the first conductive tab; a second conductive tab electrically coupled to a source of the high side MOSFET die in overlaying relationship; a low side MOSFET die coupled to the second conductive tab such that a source of the low side MOSFET die is electrically coupled to the second conductive tab; a first lead coupled to a gate of the high side MOSFET die; at least one second lead coupled to the first conductive tab; at least one third lead coupled to a source of the low side MOSFET die; a fourth lead coupled to a gate of the low side MOSFET die; and an encapsulant covering portions of the first conductive tab, the high side MOSFET die, portions of the second conductive tab, the low side MOSFET die, and portions of the first lead, the at least one second lead, the at least one third lead, and the fourth lead.
