US Patent 7487287 Time efficient embedded EEPROM/processor control method

In an embedded system with a processor and an EEPROM that provides an EEPROM BUSY signal if the EEPROM is in a write mode, a block-before-write subroutine is used to hold the processor before a write operation to the EEPROM. A detector circuit finds read functions that are to be mapped into the EEPROM address space and suspends code execution if an EEPROM BUSY bit is asserted and the EEPROM is the read target. Code execution by the processor and processor access to memories other than the EEPROM is permitted while the EEPROM is being written. If any access is made by the processor to the EEPROM while the EEPROM BUSY bit is asserted, the processor enters a WAIT state to temporarily suspends execution of program code.