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US Patent 7487419 Reduced-pin-count-testing architectures for applying test patterns

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
December 16, 2005
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Date of Patent
February 3, 2009
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Patent Application Number
11305849
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Patent Citations Received
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US Patent 12130328 Interface to full and reduced pin JTAG devices
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US Patent 11776648 Circuit for testing memory
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US Patent 11965930 Test compression in a JTAG daisy-chain environment
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US Patent 12013434 Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO
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US Patent 12117490 Scan frame based test access mechanisms
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Patent Inventor Names
Jay Jahangiri
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Wu-Tung Cheng
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Nilanjan Mukherjee
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Ronald Press
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7487419
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Patent Primary Examiner
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John P Trimmings
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