US Patent 7489010 Semiconductor memory device

In a semiconductor memory device with NAND cell units arranged, two first select gate lines in adjacent blocks sandwiching a bit line contact are formed to have first connection portions disposed at a certain pitch, where the two first select gate lines are connected to each other; two second select gate lines in adjacent blocks sandwiching a source line contact are formed to have second connection portions disposed at substantially the same pitch as the first connection portions, where the two second select gate lines are connected to each other; and the first and second shunt wirings are contacted with the first and second select gate lines at the first and second connection portions, respectively.