US Patent 7489153 Semiconductor memory device

The invention relates to a semiconductor memory device, which can be operated in a normal operating mode and a test mode, comprising: data terminals and data clock terminals; input receivers for processing the signal arriving via the respective terminal, a respective input receiver being assigned to a data terminal and/or data clock terminal; at least one test circuit, a respective test circuit being assigned to an input receiver and the test circuit being designed for determining at least one predetermined property of the assigned input receiver.