US Patent 7489752 Synchronisation of signals between asynchronous logic

A data processing apparatus comprising a plurality of data processors, each data processor comprising: first logic operable in a first clock domain and further logic operable in a second clock domain, said first and second clock domains being asynchronous with each other; a synchronizer operable to synchronize a signal processed by said first logic to produce a signal synchronized to said second clock domain; a synchronized signal output operable to export from said data processor said synchronized signal output from said synchronizer; and a signal input operable to import a signal to said data processor, said data processor being operable to route said imported signal to said further logic; wherein said plurality of data processors are arranged to operate in parallel with each other and said data processing apparatus further comprises: combining logic arranged to receive said exported synchronized signals from each of said plurality of data processors and to combine said exported synchronized signals to produce a resultant signal, said resultant signal being routed to each of said signal inputs of said plurality of data processors.