Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Nobuo Kaneko0
Koji Otsuka0
Date of Patent
February 17, 2009
0Patent Application Number
113575670
Date Filed
February 17, 2006
0Patent Primary Examiner
Patent abstract
A high electron mobility transistor is disclosed which has a double-layered main semiconductor region formed on a silicon substrate via a multilayered buffer region. The multilayered buffer region is in the form of alternations of an aluminum nitride layer and a gallium nitride layer. The main semiconductor region, buffer region, and part of the substrate taper as they extend away from the rest of the substrate, providing slanting side surfaces. An electroconductive antileakage overlay covers these side surfaces via an electrically insulating overlay. Electrically coupled to the silicon substrate via a contact electrode, the antileakage overlay serves for reduction of current leakage along the side surfaces.
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