Patent 7492238 was granted and assigned to Panasonic on February, 2009 by the United States Patent and Trademark Office.
A common terminal 500 is connected to drains of FETs 101 and 102 via a capacitor 400. FETs 111 to 114 are serially connected, and inserted between a source of the FET 101 and a terminal 501 via a capacitor 401. Similarly, each of: FETs 121 to 124; FETs 131 to 133; FETs 141 to 143; FETs 151 to 153; and FETs 161 to 163 is inserted between the source of the FET 101 or an FET 102 and a corresponding one of terminals 502 to 506. This configuration allows a stray capacitance value of a transmission/reception path to be reduced at the time of transmission/reception, thereby obtaining a favorable radio-frequency characteristic.