Patent attributes
To improve the ESD protection of a circuit receiving a signal. An inverter circuit INV1 is connected to ground wiring GND1 for supplying power, and is connected to power supply wiring VDD1 via a PMOS transistor MP5. An inverter circuit INV2 is connected to ground wiring GND2 and power supply wiring VDD2 for supplying power, and its input node is connected to an output node of the inverter circuit INV1. Further, the ground wiring GND1 and the ground wiring GND2 are connected via a protection element PE0. During normal operation, the output of an inverter circuit INV3 goes to an H level, the output of an inverter circuit INV4 goes to an L level, and the PMOS transistor MP5 is turned on. When ESD is applied, the power supply wiring VDD2 is place in a floating state, the output of the inverter circuit INV4 goes to an H level, the PMOS transistor MP5 is turned off, and a current that occurs when EDS is applied does not flow into the inverter circuit INV2.
