US Patent 7495976 Repairing integrated circuit memory arrays

A memory array 2 has an address decoder 12 responsive to a repair signal to operate either in a normal mode or a repair mode. In the normal mode a data bit is stored within a single memory cell 6. In the repair mode a data bit is stored within multiple memory cells 6 of a common column of memory cells sharing bit lines 8. This provides increased defect resistance when operating in the repair mode at the cost of reduced memory capacity.