Patent attributes
Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.
