Patent attributes
An ESD protection circuit for a semiconductor device including a bonding pad receiving a first power supply voltage; an interconnect layer provided in an underside of the bonding pad so as to be electrically conductive with the bonding pad; a semiconductor substrate provided with a first well of a predetermined conductive type in a predetermined region of a surface layer of the substrate, which first well receives a second power supply voltage having a different voltage from the first power supply voltage and provided with a confronting region confronting the underside of the interconnect layer over a dielectric layer, and the first well of the semiconductor substrate, the dielectric layer, the bonding pad and the interconnect layer constitute a capacitor.
