US Patent 7498836 Programmable low power modes for embedded memory blocks

A PLD (700) includes a plurality of logic blocks (701), a plurality of high gating circuits (702) coupled between corresponding logic blocks (701) and a supply voltage (VDD), a plurality of low gating circuits (703) coupled between corresponding logic blocks (701) and ground potential, and a plurality of control circuits (704) to provide control signals (CTRL) to the gating circuits. Each gating circuit pair selectively reduces the operating voltage provided to a corresponding logic block by one or more diode voltage drops in response to the corresponding control signal, thereby allowing the operating voltage provided to each logic block to be dynamically adjusted during run time in response to the control signals.