Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Hiroyuki Murai0
Youichi Tobita0
Date of Patent
March 3, 2009
Patent Application Number
11532750
Date Filed
September 18, 2006
Patent Citations Received
Patent Primary Examiner
Patent abstract
A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.
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