US Patent 7502273 Two-port SRAM with a high speed sensing scheme

A static random access memory (SRAM) macro includes: a cell array having one or more SRAM cells addressed by a plurality of bit lines and word lines; one or more reference cells coupled to at least one reference bit line and the word lines addressing the SRAM cells; and at least one sense amplifier having a first terminal receiving a sensing current generated by an SRAM cell selected from the cell array and a second terminal receiving a reference current generated by the reference cell controlled by the same word line coupled to the selected SRAM cell for comparing the sensing current to the reference current to generate an output signal representing a logic state of the selected SRAM cell.