US Patent 7503024 Method for hierarchical VLSI mask layout data interrogation
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Patent Inventor Names
Michael Robert Curry0
Raymond Alan Richetta0
Richard Scott Brink0
Timothy Joseph Schmerbeck0
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Patent abstract
The present disclosure is directed to a method for hierarchical Very Large Scale Integrated (VLSI) mask layout data interrogation. The method displays a tree diagram of the layout hierarchy and then allows the user to interrogate the mask layout shapes by using a cross probing feature.
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US Patent 07503024 Method for hierarchical VLSI mask layout data interrogation US Patent 7503024 Method for hierarchical VLSI mask layout data interrogation
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Patent Number
075030240
Patent Number
75030240
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Patent Jurisdiction
Patent Number
075030240
Date of Patent
March 10, 2009
0Patent Application Number
121694470
Date Filed
July 8, 2008
0Official Website
Patent Primary Examiner
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US Patent 07503024 Method for hierarchical VLSI mask layout data interrogation
Infobox
Is a
Patent jurisdiction
Patent number
07503024
Date of patent
March 10, 2009
Patent application number
12169447
Date Filed
July 8, 2008
Patent primary examiner
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