Patent attributes
A selecting circuit having minimal signal distortion caused by non-linearity of semiconductor switching elements includes a plurality of circuit groups each comprising an input terminal (INa); serially connected resistors (R1a, R2a) having a first end connected to the input terminal; a semiconductor switching element (SW1a) having a first end connected to a node between the resistors; and semiconductor switching elements (SW2a, SW3a) having first ends connected to a second end of the resistors (R1a, R2a). The circuit further includes an operational amplifier (OP) having an inverting input terminal to which second ends of semiconductor switching elements (SW1a, SW1b, . . . , SW1n) in respective ones of the circuit groups are connected in common, and an output terminal to which second ends of semiconductor switching elements (SW2a, S2b, . . . , SW2n) in respective ones of the circuit groups are connected in common; and an output terminal (OUT) to which second ends of semiconductor switching elements (SW3a, SW3b, . . . , SW3n) in respective ones of the circuit groups are connected in common.
