Patent attributes
Adjusting input power in response to a clock frequency change is disclosed. In some embodiments, a clock signal is input into a buffer, and if an increase in clock frequency is detected at the buffer input relative to the buffer output, the supplied power is increased so that an increased supplied power is provided to an associated system before the increased frequency clock signal is output from the buffer and applied to the system. In some embodiments, the current operating frequency is compared with the operating frequency associated with the next operating state. If the next operating frequency is higher than the current operating frequency, the supplied power is increased, and application of the next operating frequency is delayed so that the next operating frequency is not applied before the increased supplied power is available.
