Patent attributes
A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional modules. Moreover, the method includes receiving (106) at least an input load or an output load, or both, corresponding to the functional module. Further still, the method includes calculating (108) size of a plurality of transistors in the functional module. The system includes a characteristic table generator (302) and an optimizer unit (304). The characteristic table generator (302) generates the characteristic table. The optimizer unit (304) selects the functional module from the one or more functional modules. The optimizer unit (302) further resizes the plurality of transistors in the functional module.
