Patent attributes
A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.
