Patent attributes
A device for processing a digital input value includes a first memory portion having stored thereon Q delimiter values where the Q delimiter values divide the range of the N-bit digital input value into Q+1 regions and at least a first region and a second region are of unequal sizes, a second memory portion has stored thereon a look-up table storing Q+1 sets of coefficients for performing numerical value conversion of the digital input value to a digital output value in a second, natural unit, and an arithmetic logic performing numerical value conversion using the N-bit digital input value and the selected coefficient pair. The N-bit digital input value is compared with the Q delimiter values to determine a respective one of the Q+1 regions in which the N-bit digital input value lies. The look-up table is indexed according to the respective region to provide the selected coefficient pair.