US Patent 7511997 Semiconductor memory device

A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit, wherein each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, and each pair cell is set to have different physical quantity levels in two memory cells therein, thereby storing M-value data defined by M=2n (where M>N and “n” is an integer equal to two or more), the M-value data being defined by such M combination states that differences of the physical quantity levels in the two memory cells are different from each other.