US Patent 7514276 Aligning stacked chips using resistance assistance
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Patent Inventor Names
Corey Elizabeth Yearous0
David Paul Paulsen0
Gregory John Uhlmann0
John Edward Sheets, II0
Karl Robert Ericson0
Kelly Lynn Williams0
Phil Christopher Paone0
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Patent abstract
The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further relates to taking a resistance measurement to determine a quality of alignment wherein the resistance measurement indicates a direction in which the first chip and the second chip are misaligned.
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US Patent 07514276 Aligning stacked chips using resistance assistance US Patent 7514276 Aligning stacked chips using resistance assistance
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Patent Number
075142760
Patent Number
75142760
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Official Website
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Patent Jurisdiction
Patent Number
075142760
Date of Patent
April 7, 2009
0Patent Application Number
121903950
Date Filed
August 12, 2008
0Official Website
Patent Primary Examiner
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US Patent 07514276 Aligning stacked chips using resistance assistance
Infobox
Is a
Patent jurisdiction
Patent number
07514276
Date of patent
April 7, 2009
Patent application number
12190395
Date Filed
August 12, 2008
Patent primary examiner
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