US Patent 7514757 Memory formation with reduced metallization layers

A semiconductor structure includes a static random access memory (SRAM) cell comprising a first pull-up MOS device, a first pull-down MOS device and a first pass-gate MOS device, a first metallization layer, and an inter-layer dielectric (ILD) underlying the first metallization layer, wherein the ILD comprises an upper portion and a lower portion, a first first-layer contact in the lower portion of the ILD and connecting at least two of the first pull-up MOS device, the first pull-down MOS device and the first pass-gate MOS device. The first first-layer contact is physically isolated from second layer contacts in the upper portion of the ILD. The semiconductor structure further includes a second first-layer contact in the lower portion of the ILD, and a second-layer contact having at least a portion on the second first-layer contact, wherein the second layer contact electrically connects the second first-layer contact.