US Patent 7515656 Clock recovery circuit and data receiving circuit

A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.