Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Jin Yuan Lee0
Mou-Shiung Lin0
Date of Patent
April 14, 2009
Patent Application Number
11901079
Date Filed
September 14, 2007
Patent Primary Examiner
Patent abstract
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
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