US Patent 7517787 C4 joint reliability

Patent 7517787 was granted and assigned to Intel on April, 2009 by the United States Patent and Trademark Office.

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Patent Citations Received

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US Patent 11948876 Package structure with through vias

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Patent Inventor Names

Carlton Hanna0

Debendra Mallik0

Dongming He0

Matthew Escobido0

Sairam Agraharam0

Sujit Sharan0

Vasudeva Atluri0

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Patent abstract

In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

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Official Website

https://pdfpiw.uspto.gov/.piw?Docid=075177870

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